The reliability of semiconductor power devices and systems needs to be investigated during their design process, as well as in the qualification of final products before market release. Comprehensive life test procedures have been described in automotive and industrial standards, but future technologies require new developments in test methodology, such as:
- High power, multi-channel stress test environments for discrete and integrated power devices to cover regular as well as irregular operating conditions (e.g. power cycling, avalanche, short circuit).
- Quick and reliable overload protection to avoid damage to the test equipment in case of catastrophic device failure and retain failed samples for further physical inspection.
- Flexible embedded real-time control of test equipment, driven by a user-programmable distributed state machine environment, to enable cyclic stress testing under variable load conditions.
- Advanced condition monitoring based on in-situ data acquisition and live diagnosis of power device and system state, to detect and record individual stress-related degradation or failure events.
- Application related system level stress test environments (e.g. DC/AC power converter stages) to study robustness and reliability of power devices under real life conditions.
All KAI stress test systems are designed to cover the requirements of safe and reproducible high power testing, digital real-time control, system self test capability and in-situ condition monitoring. Raw measurement data is collected by a distributed bus system and recorded to a dynamic data base during test runs to create comprehensive reports for further statistical analysis and research on device reliability.
KAI has been developing and implementing advanced reliability test concepts, methods and equipment for power semiconductors and their applications since 2006:
- The ACUTE – "Active Cycle Universal Test Equipment" provides short circuit stress test capability according to the AEC Q100-012 standard for automotive smart power switches up to 50 V / 500 A per channel.
- The MoPS – "Modular Power Stress" test system concept provides a flexible framework for stress testing of power devices under monitored and protected conditions in a target system environment based on individual control, measurement and power modules.
- The MARS – "Modular Application Related Stress" architecture expands the MoPS concept to stress testing of power devices on system level, emulating a “real life” power electronic application system environment.
- The SAM – "Software Architecture for MoPS/MARS" is our software execution environment. It allows creating and executing control and measurement tasks for various automated test applications. The non-linear test plans are represented by distributed finite state machines (FSM) which interact with the test hardware using Lua script language.
Application-relevant stress testing on device and system level is driven by complex technology, design and customer requirements, motivating our joint research effort at KAI to provide the next generation of test concepts for power devices:
- Dynamic pulse testing of discrete power semiconductors (IGBT, MOSFET, …) at high voltage and current levels (1200 V, 100 A … 300 A) in relevant numbers (up to 100 parallel channels) for statistical significance and valid product qualification.
- Distributed real-time test control for multichannel stress test systems, based on a network of smart sensor and controller nodes linked to a flexible, user-programmable host via a high speed bus interface.
- Application-oriented stress test concepts for novel power semiconductor technologies, expanding current test system architectures and capabilities to highest switching speeds and MHz frequencies under hard and soft commutation conditions.
- High speed real-time data acquisition and processing concepts to match the fast monitoring and control requirements of dynamic power converter architectures for advanced application stress testing.
- Optimization of electrical and thermal performance of novel stress test concepts by FEM simulation of parasitic impedances and critical cooling conditions.